Amaury Graillat - amoweb.fr

I am PhD graduated from Verimag (Synchrone team, Université Grenoble Alpes) and the Kalray company. I worked under the supervision of Pascal Raymond, Matthieu Moy at Verimag and Benoît Dupont de Dinechin at Kalray.

My topic was the parallel code generation from the Synchrous data-flow languages Lustre/Scade to the Kalray MPPA many-core processor.

Research Interests

Bounding the delays of the MPPA network-on-chip with network calculus: Models and benchmarks
Marc Boyer, Amaury Graillat, Benoît Dupont de Dinechin, Jörn Migge, Performance Evaluation Journal 143: 102124, 2020.
Response Time Analysis of Dataflow Applications on a Many-Core Processor with Shared-Memory and Network-on-Chip
Amaury Graillat, Claire Maiza, Matthieu Moy, Pascal Raymond, Benoît Dupont de Dinechin, RTNS 2019 / 27th International Conference on Real-Time Networks and Systems, Toulouse, France, November 2019.
Parallel Code Generation of Synchronous Programs for a Many-core Architecture.
A. Graillat, B. Dupont de Dinechin et al. DATE 2018 – Design, Automation and Test in Europe, March 2018, Dresden, Germany. 2018
Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor.
Marc Boyer, Benoît Dupont de Dinechin, Amaury Graillat, Lionel Havet – European Congress on Embedded Real-Time Software (ERTS 2018), Toulouse, France, January 2018.
Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2-256 Processor.
B. Dupont de Dinechin & A. Graillat. 10th International Workshop on Network-on-Chip Architectures (NoCArc 2017), Boston, MA, USA
Network-on-Chip Service Guarantees on the Kalray MPPA-256 Bostan Processor.
B. Dupont de Dinechin & A. Graillat. 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing System (AISTECS 2017), Stockholm, Sweden