I am a PhD candidate at Verimag (Synchrone team, Université Grenoble Alpes) and the Kalray company. I am working under the supervision of Pascal Raymond, Matthieu Moy at Verimag and Benoît Dupont de Dinechin at Kalray.
My topic is the parallel code generation from the Synchrous data-flow languages Lustre/Scade to the Kalray MPPA many-core processor.
- Synchronous data-flow languages (Scade/Lustre)
- Parallel execution on multi-cores with real-time constraints.
- Network-on-Chip deadlock-free unicast and multicast routing algorithm.
- Quality of Service (QoS) on a network-on-Chip.
Parallel Code Generation of Synchronous Programs for a Many-core Architecture.
A. Graillat, B. Dupont de Dinechin et al. DATE 2018 – Design, Automation and Test in Europe, March 2018, Dresden, Germany. 2018
Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA2 Processor.
Marc Boyer, Benoît Dupont de Dinechin, Amaury Graillat, Lionel Havet – European Congress on Embedded Real-Time Software (ERTS 2018), Toulouse, France, January 2018.
Feed-Forward Routing for the Wormhole Switching Network-on-Chip of the Kalray MPPA2-256 Processor.
B. Dupont de Dinechin & A. Graillat. 10th International Workshop on Network-on-Chip Architectures (NoCArc 2017), Boston, MA, USA
Network-on-Chip Service Guarantees on the Kalray MPPA-256 Bostan Processor.
B. Dupont de Dinechin & A. Graillat. 2nd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing System (AISTECS 2017), Stockholm, Sweden